1. Field
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a technology for detecting an error of a command and an address.
2. Description of the Related Art
One of methods for checking an error of data transmitted/received is a parity check. The parity check indicates an error check for setting the number of data, which has a value of ‘1’, of received multi-bit data as one of an even and an odd and checking whether a data bit having a value of ‘1’ of the received multi-bit data coincides with the even or the odd. For example, in the case of an even parity check, if the number of data having a value of ‘1’ of the received multi-bit data is an even, it is determined that there is no error, and if the number of data is an odd, it is determined that there is an error. Meanwhile, in the case of an odd parity check, if the number of data having a value of ‘1’ of the received multi-bit data is an odd, it is determined that there is no error, and if the number of data is an even, it is determined that there is an error.
In a conventional memory device, the parity check has been performed in order to check whether there is an error in data. However, as the number of bits of a command signal and an address signal is increased and the transmission speed of the command signal and the address signal becomes fast, there have been increasing demands for performing the parity check for the command signal and the address signal. As a consequence, various designs for performing a parity check for a command and an address have been discussed. Therefore, a method for checking a parity of the command and the address and a method for substantially preventing the execution of a corresponding command when an error has been detected are in need.